In a chip system, a chip has a specific safe working voltage (the safe working voltage is a voltage range) at a specific frequency. Because voltage fluctuation and voltage deviation exist in a power supply system that supplies power to the chip, when the chip works at a non-safety working voltage, a timing error may occur in a digital circuit in the chip, and the timing error of the digital circuit may be a timing error on a timing path of a timing logic circuit in the digital circuit.
Currently, a probability that a timing error occurs in the digital circuit may be predicted using the following method. One prediction trigger is connected in parallel to each sampling trigger of the timing logic circuit, and a delay unit is connected before the prediction trigger (such that a timing margin of a timing path on which the prediction trigger is located is less than a timing margin of a timing path on which the sampling trigger is located), a control circuit compares a sampling result of a sampling trigger and a sampling result of a prediction trigger. If a sampling result of one sampling trigger of multiple sampling triggers in the timing logic circuit is different from a sampling result of a prediction trigger that is connected in parallel to the sampling trigger, the control circuit determines that a probability that a timing error occurs in the digital circuit is relatively high, and if sampling results of the multiple sampling triggers in the timing logic circuit are all the same as sampling results of prediction triggers that are connected in parallel to the multiple sampling triggers, the control circuit determines that a probability that a timing error occurs in the digital circuit is relatively low.
Because there are many sampling triggers in a timing logic circuit, in a process in which the foregoing method is used to determine a probability that a timing error occurs in a digital circuit, prediction triggers whose quantity is equal to a quantity of sampling triggers in the timing logic circuit are added. As a result, a large quantity of devices are used and a large chip area is occupied.